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1 lt1739 1739fas, sn1739 applicatio s u descriptio u features typical applicatio u dual 500ma, 200mhz xdsl line driver amplifier 3mm 4mm high power dfn package exceeds all requirements for full rate,downstream adsl line drivers 500ma minimum i out 11.1v output swing, v s = 12v, r l = 100 w 10.9v output swing, v s = 12v, i l = 250ma low distortion: 82dbc at 1mhz, 2v p-p into 50 w power saving adjustable supply current power enhanced tssop-20 small footprint package 200mhz gain bandwidth 600v/ m s slew rate specified at 12v and 5v high density adsl central office line drivers high efficiency adsl, hdsl2, g.lite,shdsl line drivers buffers test equipment amplifiers cable drivers the lt ? 1739 is a 500ma minimum output current, dual op amp with outstanding distortion performance. the ampli-fiers are gain-of-ten stable, but can be easily compensated for lower gains. the extended output swing allows for lower supply rails to reduce system power. supply current is set with an external resistor to optimize power dissipa- tion. the lt1739 features balanced, high impedance in- puts with low input bias current and input offset voltage. active termination is easily implemented for further sys- tem power reduction. short-circuit protection and thermal shutdown insure the devices ruggedness. the outputs drive a 100 w load to 11.1v with 12v supplies, and 10.9v with a 250ma load. the lt1739 is a pin-for-pin replacement for the lt1794 in xdsl line driverapplications and requires no circuit changes. the lt1739 is available in the very small, thermally enhanced, 3mm 4mm dfn package or a 20-lead tssop for maximum port density in central office line driverapplications. for a dual version of the lt1739, see the lt6301 data sheet. high efficiency 12v supply adsl central office line driver 1739 ta01 + C 1/2 lt1739 Cin C + 1/2 lt1739 +in 12v shdn C12v 12.7 r bias 24.9k 1:2* 110 1000pf 110 1k 1k 12.7 shdnref 100 *coilcraft x8390-a or equivalenti supply = 10ma per amplifier with r bias = 24.9k ?? , ltc and lt are registered trademarks of linear technology corporation. 4mm 3mm 0.8mm 1739 ta02 exposed thermal pad 3mm 4mm dfn package bottom view downloaded from: http:///
2 lt1739 1739fas, sn1739 order part number supply voltage (v + to v C ) ................................. 13.5v input current ..................................................... 10ma output short-circuit duration (note 2) ........... indefinite operating temperature range ............... C 40 c to 85 c specified temperature range (note 3) .. C 40 c to 85 c lt1739cfelt1739ife consult ltc marketing for parts specified with wider operating temperature ranges. absolute m axi m u m ratings w ww u package/order i n for m atio n w u u (note 1) 12 3 4 5 6 7 8 9 10 top view 2019 18 17 16 15 14 13 12 11 v C nc Cin +in shdn shdnref +in Cin nc v C v C ncout v + ncnc v + outnc v C fe package 20-lead plastic tssop t jmax = 150 c, q ja = 40 c/w, q jc = 3 c/w (note 4) underside metal connected to v C junction temperature fe package ....................................................... 150 c ue package ...................................................... 125 c storage temperature range fe package ....................................... C 65 c to 150 c ue package ...................................... C 65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number lt1739cuelt1739iue 1211 10 98 7 12 3 4 5 6 v C out av + v + out bv C Cin a+in a shdn shdnref +in bCin b top view ue12 package 12-lead (4mm 3mm) plastic dfn t jmax = 125 c, q ja = 60 c/w, q jc = 3 c/w (note 4) underside metal connected to v C electrical characteristics the denotes the specifications which apply over the full specified temperature range, otherwise specifications are at t a = 25 c. v cm = 0v, pulse tested, 5v v s 12v, v shdnref = 0v, r bias = 24.9k between v + and shdn unless otherwise noted. (note 3) symbol parameter conditions min typ max units v os input offset voltage 15 . 0 m v 7.5 mv input offset voltage matching 0.3 5.0 mv 7.5 mv input offset voltage drift 10 m v/ c i os input offset current 100 500 na 800 na i b input bias current 0.1 4 m a 6 m a input bias current matching 100 500 na 800 na e n input noise voltage density f = 10khz 8 nv/ ? hz i n input noise current density f = 10khz 0.8 pa/ ? hz ue part marking 17391739i downloaded from: http:///
3 lt1739 1739fas, sn1739 symbol parameter conditions min typ max units electrical characteristics the denotes the specifications which apply over the full specified temperature range, otherwise specifications are at t a = 25 c. v cm = 0v, pulse tested, 5v v s 12v, v shdnref = 0v, r bias = 24.9k between v + and shdn unless otherwise noted. (note 3) r in input resistance v cm = (v + C 2v) to (v C + 2v) 55 0 m w differ ential 6.5 m w c in input capacitance 3p f input voltage range (positive) (note 5) v + C 2 v + C 1 v input voltage range (negative) (note 5) v C + 1 v C + 2 v cmrr common mode rejection ratio v cm = (v + C 2v) to (v C + 2v) 74 83 db 66 db psrr power supply rejection ratio v s = 4v to 12v 74 88 db 66 db a vol large-signal voltage gain (note 8) v s = 12v, v out = 10v, r l = 40 w 63 76 db 57 db v s = 5v, v out = 3v, r l = 25 w 60 70 db 54 db v out output swing (note 8) v s = 12v, r l = 100 w 10.9 11.1 v 10.7 v v s = 12v, i l = 250ma 10.6 10.9 v 10.4 v v s = 5v, r l = 25 w 3.7 4.0 v 3.5 v v s = 5v, i l = 250ma 3.6 3.9 v 3.4 v i out maximum output current (note 8) v s = 12v, r l = 1 w 500 1200 ma i s supply current per amplifier v s = 12v, r bias = 24.9k (note 6) 8.0 10 13.5 ma 6.7 15.0 ma v s = 12v, r bias = 32.4k (note 6) 8 ma v s = 12v, r bias = 43.2k (note 6) 6 ma v s = 12v, r bias = 66.5k (note 6) 4 ma v s = 5v, r bias = 24.9k (note 6) 2.2 3.4 5.0 ma 1.8 5.8 ma supply current in shutdown v shdn = 0.4v 0.1 1 ma output leakage in shutdown v shdn = 0.4v 0.3 1 ma channel separation (note 8) v s = 12v, v out = 10v, r l = 40 w 80 110 db 77 db sr slew rate v s = 12v, a v = C 10, (note 7) 300 600 v/ m s v s = 5v, a v = C10, (note 7) 100 200 v/ m s hd2 differential 2nd harmonic distortion v s = 12v, a v = 10, 2v p-p , r l = 50 w , 1mhz C 85 dbc hd3 differential 3rd harmonic distortion v s = 12v, a v = 10, 2v p-p , r l = 50 w , 1mhz C 82 dbc gbw gain bandwidth f = 1mhz 200 mhz note 1 : absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2 : applies to short circuits to ground only. a short circuit between the output and either supply may permanently damage the part whenoperated on supplies greater than 10v. note 3 : the lt1739c is guaranteed to meet specified performance from 0 c to 85 c and is designed, characterized and expected to meet these extended temperature limits, but is not tested at C 40 c. the lt1739i is guaranteed to meet the extended temperature limits.note 4 : thermal resistance varies depending upon the amount of pc board metal attached to the device and rate of air flow over the device. if the maximum dissipation of the package is exceeded, the device will go intothermal shutdown and be protected. note 5 : guaranteed by the cmrr tests. note 6 : r bias is connected between v + and the shdn pin, with the shdnref pin grounded.note 7 : slew rate is measured at 5v on a 10v output signal while operating on 12v supplies and 1v on a 3v output signal while operating on 5v supplies. note 8 : this parameter of the lt1739cue/lt1739iue is 100% tested at room temperature, but is not tested at C40 c, 0 c or 85 c. downloaded from: http:///
4 lt1739 1739fas, sn1739 typical perfor a ce characteristics uw supply currentvs ambient temperature input common mode rangevs supply voltage input bias currentvs ambient temperature supply voltage ( v) 2 v C common mode range (v) 1.0 2.0 C2.0 4 6 81 0 1739 g02 12 C1.0 v + 0.5 1.5 C1.5 C0.5 14 t a = 25 c ? v os > 1mv temperature ( c) C50 i supply per amplifier (ma) 11 13 15 1739 g01 9 7 10 12 14 8 6 5 C30 C10 10 30 50 70 90 v s = 12v r bias = 24.9k to shdn v shdnref = 0v temperature ( c) C50 i bias (na) 120 160 200 50 1739 g03 8040 100 140 180 6020 0 C30 C10 10 30 70 90 v s = 12v i s per amplifier = 10ma input noise spectral density output short-circuit currentvs ambient temperature output saturation voltagevs ambient temperature frequency (hz) 1 input voltage noise (v/ ? hz) input current noise (pa/ ? hz) 10 1 100 1k 10k 1739 g04 0.1 10 100 1 100.1 100 100k e n i n t a = 25 c v s = 12v i s per amplifier = 10ma temperature ( c) C50 600 i sc (ma) 620 660 680 700 800740 C10 30 50 1739 g05 640 760 780 720 C30 10 70 90 v s = 12v i s per amplifier = 10ma sinking sourcing temperature ( c) C50 output saturation voltage (v) C0.5 10 1739 g06 1.0 C30 C10 30 0.5 v C v + C1.0C1.5 1.5 50 70 90 v s = 12v r l = 100 r l = 100 i load = 250ma i load = 250ma open-loop gain and phasevs frequency ?db bandwidth vs supply current slew rate vs supply current frequency (hz) C20 gain (db) phase (deg) 100 120 C40 C60 8020 6040 0 100k 10m 100m 1739 g07 C80 C160 80 120 C200 C240 40 C80 0 C40 C120 C280 1m t a = 25 c v s = 12v a v = C10 r l = 100 i s per amplifier = 10ma phase gain supply current per amplifier (ma) 2 0 C3db bandwidth (mhz) 5 15 20 25 6 8 10 12 14 45 1739 g08 10 4 30 35 40 t a = 25 c v s = 12v a v = 10 r l = 100 supply current per amplifier (ma) 2 slew rate (v/ s) 600 800 1000 11 12 1739 g09 400 200 500 700 900 300 100 0 345 67 8910 13 14 15 t a = 25 c v s = 12v a v = C10 r l = 1k rising falling downloaded from: http:///
5 lt1739 1739fas, sn1739 typical perfor a ce characteristics uw cmrr vs frequency psrr vs frequency frequency responsevs supply current frequency (mhz) 0.1 40 common mode rejection ratio (db) 50 60 70 80 1 10 100 1739 g10 30 2010 0 90 100 t a = 25 c v s = 12v i s = 10ma per amplifier frequency (mhz) 30 power supply rejection (db) 90 100 2010 8050 7060 40 0.01 1 10 100 1739 g11 C10 0 0.1 v s = 12v a v = 10 i s = 10ma per amplifier (C) supply (+) supply frequency (hz) 1k 10k 0 gain (db) 5 10 15 20 100k 1m 10m 100m 1739 g12 C5 C10C15 C20 25 30 v s = 12v a v = 10 2ma per amplifier 10ma per amplifier 15ma per amplifier output impedance vs frequency i shdn vs v shdn supply current vs v shdn frequency (mhz) 0.01 0.1 0.01 output impedance ( ) 1 1000 1 10 100 1739 g13 0.1 10 100 t a = 25 c v s 12v i s per amplifier = 2ma i s per amplifier = 10ma i s per amplifier = 15ma v shdn (v) 0 i shdn (ma) 1.5 2.0 2.5 4.0 1739 g14 1.0 0.5 0 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 t a = 25 c v s = 12v v shdnref = 0v v shdn (v) 0 supply current per amplifier (ma) 15 20 25 30 35 4.0 1739 g14 10 5 0 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 t a = 25 c v s = 12v v shdnref = 0v differential harmonic distortionvs output amplitude v out(p-p) C100 distortion (dbc) C90 C70 C60 C50 4 8 10 12 14 16 18 1739 g16 C80 02 6 C40 f = 1mhz t a = 25 c v s = 12v a v = 10 r l = 50 i s per amplifier = 10ma hd3 hd2 differential harmonic distortionvs frequency frequency (khz) distortion (dbc) C60 C50 C40 800 1739 g17 C70 C80 C65 C55 C45 C75 C85 C90 200 100 400 300 600 700 900 500 1000 v o = 10v p-p t a = 25 c v s = 12v a v = 10 r l = 50 i s per amplifier = 10ma hd3 hd2 downloaded from: http:///
6 lt1739 1739fas, sn1739 typical perfor a ce characteristics uw undistorted output swingvs frequency frequency (hz) 100k 0 output voltage (v p-p ) 5 10 15 20 300k 1m 3m 10m 1739 g19 sfdr > 40dbt a = 25 c v s = 12v a v = 10 r l = 50 i s per amplifier = 10ma +in aCin a C12v 1k 12v shdn out aout b r bias 110 out (+)out (C) 10k e in 0.01 f r l 50 1:2* 10k 49.9 110 12.7 1739 tc shdnref v C v + C + a Cin b+in b 1k 0.1 f 4.7 f 0.1 f 12v C12v C + b C12v 12.7 v out(p-p) 100 line load supply bypassing *coilcraft x8390-a or equivalentv outp-p amplitude set at each amplifier output distortion measured across line load splitter minicircuits zsc5-2-2 + + 4.7 f + 0.1 f 4.7 f test circuit differential harmonic distortionvs supply current i supply per amplifier (ma) C85 distortion (dbc) C80 C70 C65 C60 78910 C40 1739 g18 C75 23456 11 C55 C50 C45 v o = 10v p-p v s = 12v a v = 10 r l = 50 f = 1mhz, hd3 f = 1mhz, hd2 f = 100khz, hd2 f = 100khz, hd3 downloaded from: http:///
7 lt1739 1739fas, sn1739 applicatio s i for atio wu uu the lt1739 is a high speed, 200mhz gain bandwidthproduct, dual voltage feedback amplifier with high output current drive capability, 500ma source and sink. the lt1739 is ideal for use as a line driver in xdsl data communication applications. the output voltage swing has been optimized to provide sufficient headroom when operating from 12v power supplies in full-rate adsl applications. the lt1739 also allows for an adjustment ofthe operating current to minimize power consumption. in addition, the lt1739 is available in small footprint 3mm 4mm dfn and 20-lead tssop surface mount package to minimize pcb area in multiport central officedsl cards. to minimize signal distortion, the lt1739 amplifiers are decompensated to provide very high open-loop gain at high frequency. as a result each amplifier is frequency stable with a closed-loop gain of 10 or more. if a closed- loop gain of less than 10 is desired, external frequency compensating components can be used. setting the quiescent operating current power consumption and dissipation are critical concerns in multiport xdsl applications. two pins, shutdown (shdn) and shutdown reference (shdnref), are pro- vided to control quiescent power consumption and allow for the complete shutdown of the driver. the quiescent current should be set high enough to prevent distortion induced errors in a particular application, but not so high that power is wasted in the driver unnecessarily. a good starting point to evaluate the lt1739 is to set the quiescent current to 10ma per amplifier. the internal biasing circuitry is shown in figure 1. ground- ing the shdnref pin and directly driving the shdn pin with a voltage can control the operating current as seen in the typical performance characteristics. when the shdn pin is less than shdnref + 0.4v, the driver is shut down and consumes typically only 100 m a of supply current and the outputs are in a high impedance state. part to part varia-tions, however, will cause inconsistent control of the qui- escent current if direct voltage drive of the shdn pin is used. using a single external resistor, r bias , connected in one of two ways provides a much more predictable control of thequiescent supply current. figure 2 illustrates the effect on supply current per amplifier with r bias connected between the shdn pin and the 12v v + supply of the lt1739 and the approximate design equations. figure 3illustrates the same control with r bias connected between the shdnref pin and ground while the shdn pin is tiedto v + . either approach is equally effective. figure 1. internal current biasing circuitry 2k shdn shdnref to start-up circuitry 1k 1739 f01 i bias to amplifiersbias circuitry 2i i 2i 5i 25 i bias = i supply per amplifier (ma) = 64 ? i bias i shdn = i shdnref r bias (k ) 0 i supply per amplifier (ma) 10 20 30 5 15 25 10 1739 f02 7 40 70 100 130 160 190 v s = 12v v + = 12v r bias shdnshdnref r bias = ? 25.6 C 2k v + C 1.2v i s per amplifier (ma) i s per amplifier (ma) ? 25.6 v + C 1.2v r bias + 2k r bias (k ) 4 7 10 50 90 130 170 210 250 30 70 100 150 190 230 270 290 i supply per amplifier (ma) 20 25 30 35 40 1739 f03 5 10 15 0 45 v s = 12v v + = 12v r bias shdnshdnref r bias = ? 64 C 5k v + C 1.2v i s per amplifier (ma) i s per amplifier (ma) ? 64 v + C 1.2v r bias + 5k figure 2. r bias to v + current control figure 3. r bias to ground current control downloaded from: http:///
8 lt1739 1739fas, sn1739 two control inputs resistor values (k ) r shdn to v cc (12v) r shdn to v logic v logic r shdn r c1 r co 3v 40.211.5 19.1 3.3v 43.213.0 22.1 5v 60.421.5 36.5 3v 4.998.66 14.3 3.3v 6.8110.7 17.8 5v 19.620.5 34.0 v c0 h l h l v c1 hh ll 10 75 2 10 75 2 10 75 2 10 75 2 10 75 2 10 75 2 supply current per amplifier (ma) one control input resistor values (k ) r shdn to v cc (12v) r shdn to v logic v logic r shdn r c 3v 40.27.32 3.3v 43.28.25 5v 60.413.7 3v 4.995.49 3.3v 6.816.65 5v 19.612.7 v c h l 10 2 10 2 10 2 10 2 10 2 10 2 supply current per amplifier (ma) r shdn r c1 v c1 v logic 12v or v logic 0v v c0 r c0 shdnshdnref 2k r shdn r c v c v logic 12v or v logic 0v shdnshdnref 1739 f04 2k applicatio s i for atio wu uu logic controlled operating currentthe dsp controller in a typical xdsl application can have i/o pins assigned to provide logic control of the lt1739 line driver operating current. as shown in figure 4 one or two logic control inputs can set two or four different operating modes. the logic inputs add or subtract current to the shdn input to set the operating current. the one logic input example selects the supply current to be either full power, 10ma per amplifier or just 2ma per amplifier, which significantly reduces the driver power consumption while maintaining less than 2 w output impedance to frequencies less than 1mhz. this low power mode retainstermination impedance at the amplifier outputs and the line driving back termination resistors. with this termina- tion, while a dsl port is not transmitting data, it can still sense a received signal from the line across the back- termination resistors and respond accordingly. the two logic input control provides two intermediate(approximately 7ma per amplifier and 5ma per amplifier) operating levels between full power and termination modes. for proper operation of the current control cir- cuitry, it is necessary that the shdnref pin be biased at least 2v more positive than v C . in single supply applica- tions where v C is at ground potential, special attention to the dc bias of the shdnref pin is required. contact linear technology for assistance in implementing a singlesupply design with operating current control. these modes can be useful for overall system power manage- ment when full power transmissions are not necessary. shutdown and recoverythe ultimate power saving action on a completely idle port is to fully shut down the line driver by pulling the shdn pin to within 0.4v of the shdnref potential. as shown in figure 5 complete shutdown occurs in less than 10 m s and, more importantly, complete recovery from the shut downstate to full operation occurs in less than 2 m s. the biasing circuitry in the lt1739 reacts very quickly to bring theamplifiers back to normal operation. figure 4. providing logic input control of operating current v shdn shdnref = 0v amplifier output 1794 f05 figure 5. shutdown and recovery timing power dissipation and heat management xdsl applications require the line driver to dissipate asignificant amount of power and heat compared to other components in the system. the large peak to rms varia- tions of dmt and cap adsl signals require high supply voltages to prevent clipping, and the use of a step-up transformer to couple the signal to the telephone line can require high peak current levels. these requirements result in the driver package having to dissipate significant amounts of power. several multiport cards inserted into a rack in an enclosed central office box can add up to many, many watts of power dissipation in an elevated ambient temperature environment. the lt1739 has built- in thermal shutdown cir cuitry that will protect the ampli- fiers if operated at excessive temperatures, however datatransmissions will be seriously impaired. it is important in downloaded from: http:///
9 lt1739 1739fas, sn1739 the design of the pcb and card enclosure to take measuresto spread the heat developed in the driver away to the ambient environment to prevent thermal shutdown (which occurs when the junction temperature of the lt1739 exceeds 165 c). estimating line driver power dissipation figure 6 is a typical adsl application shown for thepurpose of estimating the power dissipation in the line driver. due to the complex nature of the dmt signal, which looks very much like noise, it is easiest to use the rms values of voltages and currents for estimating the driver power dissipation. the voltage and current levels shown for this example are for a full-rate adsl signal driving 20dbm or 100mw rms of power on to the 100 w telephone line and assuming a 0.5dbm insertion loss inthe transformer. the quiescent current for the lt1739 is set to 10ma per amplifier. the power dissipated in the lt1739 is a combination of thequiescent power and the output stage power when driving a signal. the two amplifiers are configured to place a differential signal on to the line. the class ab output stage in each amplifier will simultaneously dissipate power in the upper power transistor of one amplifier, while sourc-ing current, and the lower power transistor of the other amplifier, while sinking current. the total device power dissipation is then: p d = p quiescent + p q(upper) + p q(lower) p d = (v + C v C ) ? i q + (v + C v outarms ) ? i load + (v C C v outbrms ) ? i load with no signal being placed on the line and the amplifierbiased for 10ma per amplifier supply current, the quies- cent driver power dissipation is: p dq = 24v ? 20ma = 480mw this can be reduced in many applications by operatingwith a lower quiescent current value. when driving a load, a large percentage of the amplifier quiescent current is diverted to the output stage and becomes part of the load current. figure 7 illustrates the total amount of biasing current flowing between the + and C power supplies through the amplifiers as a function of load current. as much as 60% of the quiescent no load operating current is diverted to the load. applicatio s i for atio wu uu figure 6. estimating line driver power dissipation 1739 f06 + C b Cin C + a +in 12v 20ma dc shdn C12v C2v rms 17.4 24.9k C sets i q per amplifier = 10ma 1:1.7 110 1000pf 110 1k 1k 17.4 shdnref 100 3.16v rms i load = 57ma rms ?? 2v rms downloaded from: http:///
10 lt1739 1739fas, sn1739 applicatio s i for atio wu uu at full power to the line the driver power dissipation is: p d(full) = 24v ? 8ma + (12v C 2v rms ) ? 57ma rms + [|C12v C (C 2v rms )|] ? 57ma rms p d(full) = 192mw + 570mw + 570mw = 1.332w* the junction temperature of the driver must be kept lessthan the thermal shutdown temperature when processing a signal. the junction temperature is determined from the following expression: t j = t ambient ( c) + p d(full) (w) ? q ja ( c/w) q ja is the thermal resistance from the junction of the lt1739 to the ambient air, which can be minimized byheat-spreading pcb metal and airflow through the enclo- sure as required. for the example given, assuming a maximum ambient temperature of 85 c and keeping the junction temperature of the lt1739 to 140 c maximum, the maximum thermal resistance from junction to ambientrequired is: q ja max cc w cw () C . ./ = = 140 85 1 332 41 3 heat sinking using pcb metal designing a thermal management system is often a trialand error process as it is never certain how effective it is until it is manufactured and evaluated. as a general rule, the more copper area of a pcb used for spreading heat away from the driver package, the more the operating junction temperature of the driver will be reduced. the limit to this approach however is the need for very compact circuit layout to allow more ports to be imple-mented on any given size pcb. fortunately xdsl circuit boards use multiple layers ofmetal for interconnection of components. areas of metal beneath the lt1739 connected together through several small 13 mil vias can be effective in conducting heat away from the driver package. the use of inner layer metal can free up top and bottom layer pcb area for external compo- nent placement. figure 8 shows examples of pcb metal being used for heat spreading. these are provided as a reference for what might be expected when using different combinations of metal area on different layers of a pcb. these examples are with a 4-layer board using 1oz copper on each. the most effective layers for spreading heat are those closest to the lt1739 junction. the small tssop and dfn packages are very effective for compact line driver designs. both pack- ages also have an exposed metal heat sinking pad on the bottom side which, when soldered to the pcb top layer metal, directly conducts heat away from the ic junction. soldering the thermal pad to the board produces a thermal resistance from junction to case, q jc , of approximately 3 c/w. as a minimum, the area directly beneath the package on allpcb layers can be used for heat spreading. limiting the area of metal to just that of the exposed metal heat sinking pad however is not very effective, particularly if the ampli- fiers are required to dissipate significant power levels. this is shown in figure 8 for both the tssop and dfn packages. expanding the area of metal on various layers significantly reduces the overall thermal resistance. if possible, an entire unbroken plane of metal close to the heat sinking pad is best for multiple drivers on one pcb card. the addition of vias (small 13mil or smaller holes which fill during pcb plating) connecting all layers of heat spreading metal also helps to reduce operating tempera- tures of the driver. these too are shown in figure? 8. important note: the metal planes used for heat sinking the lt1739 are electrically connected to the negative supply potential of the driver, typically 12v. these planes must be isolated from any other power planes used in the board design. figure 7. i q vs i load i load (ma) C240 C200 C160 C120 C80 C40 0 40 80 120 160 200 240 total i q (ma) 10 15 20 1739 f07 50 25 *note: design techniques exist to significantly reduce this value. (see line driving back termination) downloaded from: http:///
11 lt1739 1739fas, sn1739 applicatio s i for atio wu uu figure 8. examples of pcb metal used for heat dissipation. driver package mounted on top layer.heat sink pad soldered to top layer metal. metal areas drawn to scale of package size when pcb cards containing multiple ports are insertedinto a rack in an enclosed cabinet, it is often necessary to provide airflow through the cabinet and over the cards. as seen in the graph of figure 8, this is also very effective infurther reducing the junction-to-ambient thermal resis- tance of each line driver. still air q ja tssop 100 c/w tssop 50 c/w tssop 45 c/w dfn 130 c/w package top layer 2nd layer 3rd layer bottom layer dfn 75 c/w 1739 f08a airflow (linear feet per minute, lfpm) C50 C60 reduction in q ja (%) C30 C10 0 C40 C20 200 400 600 800 1739 f08b 1000 100 0 300 500 typical reduction in q ja with laminar airflow over the device 700 900 % reduction relativeto q ja in still air downloaded from: http:///
12 lt1739 1739fas, sn1739 layout and passive componentswith a gain bandwidth product of 200mhz the lt1739 requires attention to detail in order to extract maximum performance. use a ground plane, short lead lengths and a combination of rf-quality supply bypass capacitors (i.e., 0.1 m f). as the primary applications have high drive cur- rent, use low esr supply bypass capacitors (1 m f to 10 m f). the parallel combination of the feedback resistor and gainsetting resistor on the inverting input can combine with the input capacitance to form a pole that can cause frequency peaking. in general, use feedback resistors of 1k or less. compensation the lt1739 is stable in a gain 10 or higher for any supplyand resistive load. it is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. figure? 9 shows that for inverting gains, a resistor from the inverting node to ac ground guarantees stability if the parallel combination of r c and r g is less than or equal to r f /9. for lowest distortion and dc output offset, a series capacitor, c c , can be used to reduce the noise gain at lower frequencies. the break frequency produced by r c and c c should be less than 5mhz to minimize peaking. figure 10 shows compensation in the noninverting con-figuration. the r c , c c network acts similarly to the invert- ing case. the input impedance is not reduced because thenetwork is bootstrapped. this network can also be placed between the inverting input and an ac ground. another compensation scheme for noninverting circuits is shown in figure 11. the circuit is unity gain at low frequency and a gain of 1 + r f /r g at high frequency. the dc output offset is reduced by a factor of ten. thetechniques of figures 10 and 11 can be combined as shown in figure 12. the gain is unity at low frequencies, 1 + r f /r g at mid-band and for stability, a gain of 10 or greater at high frequencies. figure 9. compensation for inverting gains applicatio s i for atio wu uu r g r c v o v i c c (optional) C + 1739 f09 r f = Cr f r g v o v i < 5mhz 1 2 r c c c (r c || r g ) r f /9 r c v o v i c c (optional) + C 1739 f10 r f r g = 1 + r f r g v o v i < 5mhz 1 2 r c c c (r c || r g ) r f /9 figure 10. compensation for noninverting gains + C 1739 f11 r f r g v i v o c c < 5mhz 1 2 r g c c r g r f /9 = 1 (low frequencies) (high frequencies) v o v i = 1 + r f r g figure 11. alternate noninverting compensation r c v o v i c c + C 1739 f12 r f r g c big r f r g = 1 at low frequencies = 1 + at medium frequencies r f (r c || r g ) = 1 + at high frequencies v o v i figure 12. combination compensation downloaded from: http:///
13 lt1739 1739fas, sn1739 in differential driver applications, as shown on the firstpage of this data sheet, it is recommended that the gain setting resistor be comprised of two equal value resistors connected to a good ac ground at high frequencies. this ensures that the feedback factor of each amplifier remains less than 0.1 at any frequency. the midpoint of the resistors can be directly connected to ground, with the resulting dc gain to the v os of the amplifiers, or just bypassed to ground with a 1000pf or larger capacitor.line driving back-termination the standard method of cable or line back-termination is shown in figure 13. the cable/line is terminated in its characteristic impedance (50 w , 75 w , 100 w , 135 w , etc.). a back-termination resistor also equal to the chararacteristicimpedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. there are three main drawbacks to this approach. first, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is wasted in the termination resistor. second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. the increase in gain increases noise and decreases bandwidth (which can also increase distortion). third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage. an alternate method of back-termination is shown in figure 14. positive feedback increases the effective back- termination resistance so r bt can be reduced by a factor of n. to analyze this circuit, first ground the input. as r bt ?= r l /n, and assuming r p2 >>r l we require that: d v a = d v o (1 C 1/n) to increase the effective value of r bt by n. d v p = d v o (1 C 1/n)/(1 + r f /r g ) d v o = d v p (1 + r p2 /r p1 ) applicatio s i for atio wu uu + C 1739 f13 r f r bt cable or line with characteristic impedance r l r g v o v i r l (1 + r f /r g ) = v o v i 12 r bt = r l figure 13. standard cable/line back termination + C 1739 f14 r f r bt r p2 r p1 r g v i v a v p v o r l r f r g 1 + r l n = v o v i = 1 C C 1n for r bt = () r f r g 1 + () r p1 r p1 + r p2 r p1 r p2 + r p1 r p2 /(r p2 + r p1 ) () 1 + 1/n figure 14. back termination using postive feedback eliminating d v p , we get the following: (1 + r p2 /r p1 ) = (1 + r f /r g )/(1 C 1/n) for example, reducing r bt by a factor of n = 4, and with an amplifer gain of (1 + r f /r g ) = 10 requires that r p2 /r p1 =? 12.3. note that the overall gain is increased: v v rrr nr rrrr o i ppp fg p p p = + () + () + () [] -+ () [] 221 12 1 11 1 / // / / downloaded from: http:///
14 lt1739 1739fas, sn1739 applicatio s i for atio wu uu a simpler method of using positive feedback to reduce theback-termination is shown in figure 15. in this case, the drivers are driven differentially and provide complemen- tary outputs. grounding the inputs, we see there is invert- ing gain of Cr f /r p from Cv o to v a d v a = d v o (r f /r p ) and assuming r p >> r l , we require d v a = d v o (1 C 1/n) solving r f /r p = 1 C 1/n so to reduce the back-termination by a factor of 3 chooser f /r p = 2/3. note that the overall gain is increased to: v o /v i = (1 + r f /r g + r f /r p )/[2(1 C r f /r p )] using positive feedback is often referred to as activetermination. figure 18 shows a full-rate adsl line driver incorporating positive feedback to reduce the power lost in the back termination resistors by 40% yet still maintains the proper impedance match to the100 w characteristic line imped- ance. this circuit also reduces the transformer turns ratio over the standard line driving approach resulting in lowerpeak current requirements. with lower current and less power loss in the back termination resistors, this driver dissipates only 1w of power, a 30% reduction. (additional power savings are possible by further reducing the termi- nation resistors value). while the power savings of positive feedback are attractive there is one important system consideration to be ad- dressed, received signal sensitivity. the signal received from the line is sensed across the back termination resis- tors. with positive feedback, signals are present on both ends of the r bt resistors, reducing the sensed amplitude. extra gain may be required in the receive channel tocompensate, or a completely separate receive path may be implemented through a separate line coupling transformer. a demo board, dc306a-c, is available for the lt1739cfe. this demo board is a complete line driver with an lt1361 receiver included. it allows the evaluation of both standard and active termination approaches. it also has circuitry built in to evaluate the effects of operating with reduced supply current. the schematic of this demo board is shown in figure 17. considerations for fault protection the basic line driver design, shown on the front page ofthis data sheet, presents a direct dc path between the outputs of the two amplifiers. an imbalance in the dc biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a dc voltage differential between the two amplifier outputs. this condition can force a considerable amount of current to flow as it is limited only by the small valued back-termination resistors and the dc resistance of the transformer primary. this high current can possibly cause the power supply voltage source to drop significantly impacting overall system performance. if left unchecked, the high dc current can heat the lt1739 to thermal shutdown. C + r bt r f r g r p r p r g r l r l Cv i v a Cv a v i Cv o v o C + r bt 1739 f15 r f r l n = v o v i n = 1 C 2 for r bt = r f r p r f r p + r f r g 1 + 1 C r f r p 1 () figure 15. back termination using differential postive feedback downloaded from: http:///
15 lt1739 1739fas, sn1739 using dc blocking capacitors, as shown in figure 16, toac couple the signal to the transformer eliminates the possibility for dc current to flow under any conditions. these capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission. another important fault related concern has to do with very fast high voltage transients appearing on the tele- phone line (lightning strikes for example). transzorbs ? , varistors and other transient protection devices are oftenused to absorb the transient energy, but in doing so also 1739 f16 + C 1/2 lt1739 Cin C + 1/2 lt1739 +in 12v shdn C12v 12.7 0.1 f 12v C12v 24.9k 1:2 lineload 110 1000pf 110 1k 1k 12.7 shdnref ?? 0.1 f 12v C12v bav99 bav99 figure 16. protecting the driver against load faults and line transients create fast voltage transitions themselves that can becoupled through the transformer to the outputs of the line driver. several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. while the lt1739 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. external clamping diodes, such as bav99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs. transzorb is a registered trademark of general instruments, gsi applicatio s i for atio wu uu downloaded from: http:///
16 lt1739 1739fas, sn1739 2 12 9 19 1739 sd + + C + C + C + C + C + + C 20 10 11 1 1 v dd v ee on/off on 1 2 3 jp3 gnd out in lt1121cst-5 sot233 c21 f 25v3216 c31 f 25v3216 + c510 f 35v7343 + c71 f 25v3216 c40.1 f 25v0603 c60.1 f c1 0.1 f c9 0.1 f c13 0.1 f c14 0.1 f c111 f 25v3216 c100.1 f + 5v v dd v cc v cc v cc v ee v ee e1v cc e3gnd e4line (+) e2 drv (+) e8 drv (C) e10 on/off e11 v c0ntrol e7rcv in (+) e13 rcv in (C) e12rcv (C) e9rcv (+) e5line (C) e6v ee place c4 and c5 as close to u2 as possible u1 c8 0.1 f 100v c12 0.1 f 100v 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 10 coilcraft x8504-a u3a lt1361cs8 u3b lt1361cs8 u4a lt1541cs8 u4b lt1541cs8 14 17 18 r210k r13 10k r18 10k r2210k r2110k r23opt r25 107 r24 107 r5 opt c15opt r15opt r26opt c17opt c16 1000pf c18opt 1206 jp6 jp5 jp4 jp2 r3 1k r6 2.49k r4 2.49k r7 1k u2a lt1739cfe u2b lt1739cfe v bias v bias adj fixed q1fmmt3904 r1721.5k r8 15.4 1/2w 2010 r11 1.6k r14 1.6k r101k r19 1k r16 1k r12 1k r209.31k 13 r1 15.4 1/2w 2010 jp1 r910k figure 17. lt1739, lt1361 adsl demo board (dc306a-c) applicatio s i for atio wu uu downloaded from: http:///
17 lt1739 1739fas, sn1739 Cin v + q1 q5 r1 v C +in out q2 q3 q12 q4 q7q8 q6 q16 q17 q15 q14 q9 c2 c1 q13 q18 1739 ss q10 q11 (one amplifier shown) si plified sche atic ww downloaded from: http:///
18 lt1739 1739fas, sn1739 u package descriptio fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ca fe20 (ca) tssop 0203 0.09 C 0.20 (.0036 C .0079) 0 C 8 recommended solder pad layout 0.45 C 0.75 (.018 C .030) 4.30 C 4.50* (.169 C .177) 6.40 bsc 134 5 6 7 8910 11 12 14 13 6.40 C 6.60* (.252 C .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment downloaded from: http:///
19 lt1739 1739fas, sn1739 u package descriptio ue12 package 12-lead plastic dfn (3mm 4mm) (reference ltc dwg # 05-08-1695) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note:1. drawing proposed to be made is a variation of version (wged) in jedec package outline m0-229 2. all dimensions are in millimeters3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 4. exposed pad shall be solder plated 0.38 0.10 bottom viewexposed pad 1.70 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 0.23 0.05 3.30 0.10 (2 sides) 1 6 12 7 0.50bsc pin 1notch pin 1 top mark 0.200 ref 0.00 C 0.05 (ue12) dfn 0102 0.23 0.05 3.30 0.05 (2 sides) recommended solder pad pitch and dimensions 1.70 0.05 (2 sides) 2.24 0.05 0.50bsc 0.58 0.05 3.40 0.05 information furnished by linear technology corporation is believed to be accurate and reliable.however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
20 lt1739 1739fas, sn1739 part number description comments lt1361 dual 50mhz, 800v/ m s op amp 15v operation, 1mv v os , 1 m a i b lt1794 dual 500ma, 200mhz xdsl line driver adsl co driver, extended output swing, low power lt1795 dual 500ma, 50mhz current feedback amplifier shutdown/current set function, adsl co driver lt1813 dual 100mhz, 750v/ m s, 8nv/ ? hz op amp low noise, low power differential receiver, 4ma/amplifier lt1886 dual 200ma, 700mhz op amp 12v operation, 7ma/amplifier, adsl modem line driver lt1969 dual 200ma, 700mhz op amp with power control 12v operation, msop package, adsl modem line driver lt6300 dual 500ma, 200mhz xdsl line driver adsl co driver in ssop package ? linear technology corporation 2001 lt/tp 0602 1.5k rev a ? printed in the usa related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com figure 18. adsl line driver using active termination u typical applicatio 1739 f17 + C 1/2 lt1739 Cin C + 1/2 lt1739 +in 12v shdn C12v 13.7 24.9k 1:1.2* 182 1000pf 182 1k 1.65k1.65k 1k 13.7 shdnref 100 line *coilcraft x8502-a or equivalent 1w driver power dissipation 1.15w power consumption ?? downloaded from: http:///

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